This application claims priority to Korean Patent Application No. 10-2004-0086131, filed on Oct. 27, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to an interface circuit for adaptively latching a data input/output signal by monitoring a data strobe signal provided by a memory device, and a memory system including the interface circuit.
2. Description of the Related Art
Memory systems commonly include a memory controller which controls operation of a memory device, such as a synchronous DRAM (SDRAM) device. The SDRAM and the memory controller perform their operations in response to a clock signal. In particular, the memory controller includes a delay locked loop (hereinafter, referred to as DLL) to stably latch data read from the SDRAM. The DLL synchronizes a data strobe signal DQS received from the SDRAM with a phase of data read from the SDRAM.
FIG. 1 is a block diagram of a conventional memory system 100. Referring to FIG. 1, a memory controller 110 and an SDRAM 120 of the memory system 100 are connected to each other through a clock signal CLK, an address signal ADDR, a data strobe signal DQS, a data input/output signal DQ[31:0], and control signals. The SDRAM 120 produces the data strobe signal DQS that has a phase that is shifted with respect to a phase of the clock signal CLK received from the memory controller 110, and provides the data strobe signal DQS to the memory controller 110. The data strobe signal DQS is produced in a delay-locked loop DLL 122 of the SDRAM 120 so as to be output in synchronization with the data input/output signal DQ[31:0]. The data strobe signal DQS is provided to a DLL 112 of the memory controller 110. The DLL 112 controls a phase of the data strobe signal DQS to latch the data input/output signal DQ[31:0] read from the SDRAM 120.
The DLL 122 of the SDRAM 120 locks the clock signal CLK, which is always received from the memory controller 110. However, the DLL 112 of the memory controller 110 locks the data strobe signal DQS, which is generated when the SDRAM 120 reads out the data input/output signal DQ[31:0]. In other words, because the DLL 112 of the memory controller 110 is required to lock the data strobe signal DQS that is arbitrarily generated, the design and implementation of a circuit for monitoring the data strobe signal DQS is not straightforward. Also, because the DLL 112 consumes a large amount of power when operating, it is not optimal for use in a memory controller 110 installed in a mobile electronic device, such as, a cellular phone.